As CMOS transistor scaling proceeds into the deep sub-micron regime, the signal integration of many active elements has necessitated that many layers of high density metal interconnect. To reduce device resistance and capacitance (“RC”), the industry has moved away from aluminum interconnect metal with silicon dioxide dielectric between the metal lines to copper coupled with low-K interlayer dielectric (“ILD”) materials in single and dual damascene structures. Copper metallization combined with low dielectric constant (“low-k”) ILDs has resulted in the reduction of RC time constant delays in interconnect devices. This integration of copper with low-k materials is considered to be critical to the development of next-generation ultra-large-scale integrated circuit technologies. A variety of copper and low-k approaches and integration schemes are currently being explored.
Single and dual damascene processes are well-detailed in the literature (for example, see Steinbruchel, Christoph and Barry L. Chin, “Copper Interconnect Technology,” SPIE Press, 2001). Briefly described, in a dual damascene process, both the via and trenches are etched in the dielectric layer overlying an underlying interconnect or trace. The desired metal is then deposited into the trenches and holes in one step to form a dual damascene structure. Chemical mechanical polishing (“CMP”) is used to remove the unwanted surface metal, while leaving the desired metal in the trenches and holes, thus forming in-laid interconnect lines and vias that are coupled to electrical components beneath the insulation layer. The goal of CMP processing is to leave a planarized surface for subsequent metallization to build multi-level interconnections.
However, there exist special challenges for fabricating damascene structures made of copper inlay and low-k ILD materials that cannot be corrected by CMP processing. Surface irregularities and other topography issues such as dishing or erosion created during the etching, ashing, resist removal, and cleaning steps are potentially more damaging in dual-damascene than in non-damascene processes. Unlike aluminum processes, where CMP flattens out the dielectric before patterning, there is no topography correction in dual-damascene. Therefore, if a dip is created at metal 1, it will be transferred into the dielectric creating a dip at metal two, and create a potential short. Thus, critical to the damascene process are vertical via profiles with smooth side walls, particularly in a via-first damascene process. If the via is sloped, residual resist or hard mask can form a “fence” that can partially block the etch, thus rounding the edges of the via and reducing the cross-sectional area of copper from the line into the via. Fencing may also be formed during the trench etch step due to a thick gap-fill (e.g., BARC gap fill material) and with the use of highly polymerizing plasma etch chemistries.
Typical damascene structures used in leading-edge devices with up to eight levels of metal incorporate a barrier metal such as Ta/TaN that surround the copper on all sides, followed by a seed layer copper deposition and copper electroplating. Optimization of the process is needed to assure adequate barrier metal step coverage in preparation for bottom-up fill by copper electroplating. Typical etching and ashing techniques result in the pullback (erosion) of the dielectric film, and an increase in the effective k, particularly for low-k materials.
FIG. 1A shows an intermediate structure created during a conventional copper dual damascene process after via and trench etching has been completed and just prior to barrier metal and copper seed deposition. This structure shows an undercut hard mask layer 14 that protrudes slightly into the trench opening 26. The hard mask layer 14 lies over the trench sidewalls which comprise low-K ILD 20. Within the via openings 28 are conductive structures 24 which are covered with a copper diffusion barrier layer 22.
Typically, the stripping and etching involved in the via and trench formation will cause a portion of the dielectric layer 20 lying beneath the hard mask 14 to be eroded such that an undercut of the hard mask results. Thus, when a barrier metal layer 30 is formed on the via opening and trench opening with conductive materials such as copper (e.g., copper seeding followed by electroplating with copper atoms), as shown in FIG. 1B, the irregularity in the sidewall of the trench results in a discontinuity of the barrier metal layer 30 (e.g., electroplating of conductive atoms does not occur at the site of the discontinuity and thus a nonconformal coating results). FIG. 1C shows the structure after metal deposition is completed and has undergone planarization by CMP. However, the resulting damascene structure exhibits failure (e.g. voids) at the surface interface between the copper feature 32 and the dielectric layer 20. Such defects in the surface result in electromigration resistance within the structure and pose performance and reliability issues in the finished devices.
Thus, while the conventional damascene processes are workable, there remains room for improvement. It would be desirable to provide a process for the formation of void-free damascene structures with precise planarization.